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K4T51043QE K4T51083QE K4T51163QE
DDR2 SDRAM
512Mb E-die DDR2 SDRAM Specification
60FBGA & 84FBGA with Pb-Free (RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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DDR2 SDRAM
Table of Contents
1.0 Ordering Information ....................................................................................................................4 2.0 Key Features .................................................................................................................................4 3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5 3.1 x4 package pinout (Top View) : 60ball FBGA Package ........................................................................5 3.2 x8 package pinout (Top View) : 60ball FBGA Package .........................................................................6 3.3 x16 package pinout (Top View) : 84ball FBGA Package .......................................................................7 3.4 FBGA Package Dimension(x4/x8) .....................................................................................................8 3.5 FBGA Package Dimension(x16) .......................................................................................................9 4.0 Input/Output Functional Description ........................................................................................10 5.0 DDR2 SDRAM Addressing .........................................................................................................11 6.0 Absolute Maximum DC Ratings .................................................................................................12 7.0 AC & DC Operating Conditions .................................................................................................12 .......................................................................12 7.2 Operating Temperature Condition ..................................................................................................13 7.3 Input DC Logic Level ....................................................................................................................13 7.4 Input AC Logic Level ....................................................................................................................13 7.5 AC Input Test Conditions ..............................................................................................................13 7.6 Differential input AC logic Level .....................................................................................................14 7.7 Differential AC output parameters ..................................................................................................14 8.0 ODT DC electrical characteristics .............................................................................................14 9.0 OCD default characteristics ......................................................................................................15 10.0 IDD Specification Parameters and Test Conditions ..............................................................16 11.0 DDR2 SDRAM IDD Spec ...........................................................................................................18 12.0 Input/Output capacitance .........................................................................................................19 13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................19 13.1 Refresh Parameters by Device Density ........................................................................................19 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................19 13.3 Timing Parameters by Speed Grade ............................................................................................20 14.0 General notes, which may apply for all AC parameters ........................................................22 15.0 Specific Notes for dedicated AC parameters ..........................................................................23
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
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DDR2 SDRAM
Year 2006 2006 2006 2006 2006 2007 2007 2007 2007 - Initial Release - Revised the IDD values - Revised the IDD values - Added DDR2-800 CL6 - Added the detailed explanation on the notes for AC parameters - Corrected Typo - Added data setup and hold time derating values for single-end DQS - Corrected Typo - Corrected Typo - Updated general and specific notes for AC parameters History
Revision History
Revision 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Month March August September September October March April June July
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K4T51043QE K4T51083QE K4T51163QE 1.0 Ordering Information
Org. 128Mx4 64Mx8 32Mx16 DDR2-800 5-5-5 K4T51043QE-ZC(L)E7 K4T51083QE-ZC(L)E7 K4T51163QE-ZC(L)E7 DDR2-800 6-6-6 K4T51043QE-ZC(L)F7 K4T51083QE-ZC(L)F7 K4T51163QE-ZC(L)F7 DDR2-667 5-5-5 K4T51043QE-ZC(L)E6 K4T51083QE-ZC(L)E6 K4T51163QE-ZC(L)E6 DDR2-533 4-4-4
DDR2 SDRAM
DDR2-400 3-3-3 Package 60 FBGA 60 FBGA 84 FBGA
K4T51043QE-ZC(L)D5 K4T51043QE-ZC(L)CC K4T51083QE-ZC(L)D5 K4T51083QE-ZC(L)CC K4T51163QE-ZC(L)D5 K4T51163QE-ZC(L)CC
Note : 1. Speed bin is in order of CL-tRCD-tRP 2. RoHS Compliant
2.0 Key Features
Speed CAS Latency tRCD(min) tRP(min) tRC(min) DDR2-800 5-5-5 5 12.5 12.5 57.5 DDR2-800 6-6-6 6 15 15 60 DDR2-667 5-5-5 5 15 15 60 DDR2-533 4-4-4 4 15 15 60 DDR2-400 3-3-3 3 15 15 55 Units tCK ns ns ns
* JEDEC standard 1.8V 0.1V Power Supply * VDDQ = 1.8V 0.1V * 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/ pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/ sec/pin * 4 Banks * Posted CAS * Programmable CAS Latency: 3, 4, 5, 6 * Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5 * Write Latency(WL) = Read Latency(RL) -1 * Burst Length: 4 , 8(Interleave/nibble sequential) * Programmable Sequential / Interleave Burst Mode * Bi-directional Differential Data-Strobe (Single-ended datastrobe is an optional feature) * Off-Chip Driver(OCD) Impedance Adjustment * On Die Termination * Special Function Support -PASR(Partial Array Self Refresh) -50ohm ODT -High Temperature Self-Refresh rate enable * Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95 C * All of Lead-free products are compliant for RoHS
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed doubledata-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/ CAS multiplexing style. For example, 512Mb(x4) device receive 14/11/2 addressing. The 512Mb DDR2 device operates with a single 1.8V 0.1V power supply and 1.8V 0.1V VDDQ. The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16).
Note : The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in "Samsung's DDR2 SDRAM Device Operation & Timing Diagram"
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K4T51043QE K4T51083QE K4T51163QE 3.0 Package Pinout/Mechanical Dimension & Addressing
DDR2 SDRAM
3.1 x4 package pinout (Top View) : 60ball FBGA Package
1
VDD NC VDDQ NC VDDL
2
NC VSSQ DQ1 VSSQ VREF CKE
3
VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L
7
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
8
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
9
VDDQ NC VDDQ NC VDD ODT
NC
BA0 A10/AP
VDD
VSS
A3 A7
VSS
VDD
A12
Note : 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x4)
: Populated Ball + : Depopulated Ball Top View (See the balls through the Package)
1 A B C D E F G H J K L 2 3 4 5 6 7 8 9
+ + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + +
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DDR2 SDRAM
3.2 x8 package pinout (Top View) : 60ball FBGA Package
1
VDD DQ6 VDDQ DQ4 VDDL
2
NU/ RDQS VSSQ DQ1 VSSQ VREF CKE
3
VSS DM/ RDQS VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L
7
VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
8
DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13
9
VDDQ DQ7 VDDQ DQ5 VDD ODT
NC
BA0 A10/AP
VDD
VSS
A3 A7
VSS
VDD
A12
Note : 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. 3. The function of DM or RDQS/RDQS are enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL.
Ball Locations (x8)
: Populated Ball + : Depopulated Ball Top View (See the balls through the Package)
1 2 3 4 5 6 7 8 9 A B C D E F G H J K L
+ + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + + + + + + + + + +
+ + +
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DDR2 SDRAM
3.3 x16 package pinout (Top View) : 84ball FBGA Package
1
VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL
2
NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE
3
VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L M N P R
7
VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC
8
UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC
9
VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT
NC
BA0 A10/AP
VDD
VSS
A3 A7
VSS
VDD
A12
Note : 1. VDDL and VSSDL are power and ground for the DLL. 2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
1
2
3
4
5
6
7
8
9
Ball Locations (x16)
: Populated Ball + : Depopulated Ball
A B C D E F
Top View (See the balls through the Package)
G H J K L M N P R
+ + +
+ + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + +
+ + +
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DDR2 SDRAM
3.4 FBGA Package Dimension(x4/x8)
9.00 0.10 0.80 x 8 = 6.40 3.20 0.80 1.60 6 5 4 3 2 1 # A1 INDEX MARK
A
B
(Datum A)
9
8
7
A B
D E F
0.80
(Datum B)
C 0.80 x 10 = 8.00 4.00
H J K L
(0.95) 60-0.45 Solder ball (Post reflow 0.50 0.05) 0.2 M A B (1.90) MOLDING AREA
Bottom
0.10MAX
9.00 0.10 #A1
0.80
G
11.00 0.10 11.00 0.10
0.35 0.05 1.10 0.10
Top
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3.5 FBGA Package Dimension(x16)
9.00 0.10 0.80 x 8 = 6.40 3.20 0.80 1.60 6 5 4 3 2 1 # A1 INDEX MARK
A
B
(Datum A)
A B
9
8
7
D E
0.80 x 14 = 11.20 5.60
F G H 0.80 J K L M N P R
0.80
(Datum B)
C
(0.95) 84-0.45 Solder ball (Post reflow 0.50 0.05) 0.2 M A B (1.90) MOLDING AREA
Bottom
0.10MAX
9.00 0.10 #A1
13.00 0.10 13.00 0.10
0.35 0.05 1.10 0.10
Top
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K4T51043QE K4T51083QE K4T51163QE 4.0 Input/Output Functional Description
Symbol CK, CK Type Input Function
DDR2 SDRAM
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2. The address inputs also provide the opcode during Mode Register Set commands. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. A control bit at EMRS(1)[A10] enables or disables all complementary data strobe signals.
CKE
Input
CS
Input
ODT
Input
RAS, CAS, WE DM (UDM), (LDM)
Input
Input
BA0 - BA1
Input
A0 - A13
Input
DQ
Input/Output Data Input/ Output: Bi-directional data bus.
DQS, (DQS) In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) (LDQS), (LDQS) Input/Output x4 DQS/DQS (UDQS), (UDQS) x8 DQS/DQS if EMRS(1)[A11] = 0 (RDQS), (RDQS) x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1 x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x4 DQS x8 DQS if EMRS(1) [A11] = 0 x8 DQS, RDQS, if EMRS(1) [A11] = 1 x16 LDQS and UDQS NC VDD/VDDQ VSS/VSSQ VDDL VSSDL VREF Supply Supply Supply Supply Supply No Connect: No internal electrical connection is present. Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V Ground, DQ Ground DLL Power Supply: 1.8V +/- 0.1V DLL Ground Reference voltage
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512Mb
Configuration # of Banks Bank Address Auto precharge Row Address Column Address 128Mb x4 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9,A11 64Mb x 8 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9
DDR2 SDRAM
32Mb x16 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9
* Reference information: The following tables are address mapping information for other densities.
256Mb
Configuration # of Banks Bank Address Auto precharge Row Address Column Address 64Mb x4 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9,A11 32Mb x 8 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9 16Mb x16 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A8
1Gb
Configuration # of Banks Bank Address Auto precharge Row Address Column Address 256Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9,A11 128Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9 64Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A12 A0 ~ A9
2Gb
Configuration # of Banks Bank Address Auto precharge Row Address Column Address 512Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9,A11 256Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9 128Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9
4Gb
Configuration # of Banks Bank Address Auto precharge Row Address Column Address/page size 1 Gb x4 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9,A11 512Mb x 8 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9 256Mb x16 8 BA0 ~ BA2 A10/AP A0 - A14 A0 - A9
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K4T51043QE K4T51083QE K4T51163QE 6.0 Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
DDR2 SDRAM
Units V V V V C Notes 1 1 1 1 1, 2
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
7.0 AC & DC Operating Conditions
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Parameter Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
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7.2 Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C
DDR2 SDRAM
Notes 1, 2
Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
7.3 Input DC Logic Level
Symbol VIH(DC) VIL(DC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
7.4 Input AC Logic Level
Symbol VIH (AC) VIL (AC) Parameter AC input logic high AC input logic low DDR2-400, DDR2-533 Min. VREF + 0.250 Max. VREF - 0.250 DDR2-667, DDR2-800 Min. VREF + 0.200 VREF - 0.200 Max. Units V V
7.5 AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
Note : 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
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7.6 Differential input AC logic Level
Symbol VID(AC) VIX(AC) Parameter AC differential input voltage AC differential cross point voltage Min. 0.5 0.5 * VDDQ - 0.175 Max. VDDQ + 0.6
DDR2 SDRAM
Units V V Notes 1 2
0.5 * VDDQ + 0.175
Note : 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH (AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
VDDQ VTR VCP VSSQ
< Differential signal levels >
VID
Crossing point
VIX or VOX
7.7 Differential AC output parameters
Symbol VOX(AC) Parameter AC differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Note 1
Note : 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
8.0 ODT DC electrical characteristics
PARAMETER/CONDITION Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm Deviation of VM with respect to VDDQ/2 Note : 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff) : Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I( VIL (ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18 VIH (ac) - VIL (ac) SYMBOL Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM MIN 60 120 40 -6 NOM 75 150 50 MAX 90 180 60 +6 UNITS ohm ohm ohm % NOTES 1 1 1 1
Rtt(eff) =
I(VIH (ac)) - I(VIL (ac))
delta VM =
2 x Vm VDDQ
-1
x 100%
Measurement Definition for VM: Measure voltage (VM) at test pin (midpoint) with no load.
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K4T51043QE K4T51083QE K4T51163QE 9.0 OCD default characteristics
Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) Sout Parameter Min Nom Max
DDR2 SDRAM
Unit ohms ohms ohms V/ns Notes 1,2 6 1,2,3 1,4,5,6,7,8
Normal 18ohms See full strength default driver characteristics 0 0 1.5 1.5 4 5
2. Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ- 280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from VIL(AC) to VIH(AC). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process and represents only the DRAM uncertainty. Output slew rate load : VTT
25 ohms Output (VOUT) Reference Point
7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin, 667Mb/sec/pin and 800Mb/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
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K4T51043QE K4T51083QE K4T51163QE 10.0 IDD Specification Parameters and Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5)
Symbol IDD0 Proposed Conditions
DDR2 SDRAM
Units mA
Notes
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; Fast PDN Exit MRS(12) = 0mA All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus Slow PDN Exit MRS(12) = 1mA inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal Low Power
IDD1
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA mA mA mA
IDD3P
IDD3N
IDD4W
mA
IDD4R
mA
IDD5B
mA mA mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
mA
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Note : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. For purposes of IDD testing, the following parameters are utilized DDR2-800 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD)-x4/x8 tRRD(IDD)-x16 tCK(IDD) tRASmin(IDD) tRP(IDD) tRFC(IDD) 5-5-5 5 12.5 57.5 7.5 10 2.5 45 12.5 105 DDR2-800 6-6-6 6 15 60 7.5 10 2.5 45 15 105 DDR2-667 5-5-5 5 15 60 7.5 10 3 45 15 105 DDR2-533 4-4-4 4 15 60 7.5 10 3.75 45 15 105 DDR2-400 3-3-3 3 15 55 7.5 10 5 40 15 105 Units tCK ns ns ns ns ns ns ns ns
Detailed IDD7 The detailed timings are shown below for IDD7. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Timing Patterns for 4 bank devices x4/ x8/ x16 -DDR2-400 3/3/3 A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D -DDR2-533 4/4/4 A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D -DDR2-667 5/5/5 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D -DDR2-800 6/6/6 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D -DDR2-800 5/5/5 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
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128Mx4 (K4T51043QE) Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 8 215 8 35 40 30 12 55 120 130 115 4 8 215 800@CL=5 CE7 85 95 5 8 35 40 30 12 55 120 130 115 4 8 180 LE7 800@CL=6 CF7 85 95 5 8 35 40 30 12 55 105 115 110 4 8 180 LF7 667@CL=5 CE6 75 85 5 8 30 35 30 12 50 90 100 105 4 8 180 LE6 533@CL=4 CD5 75 85 4.5 8 30 35 30 12 50 80 90 105 4 LD5 400@CL=3 CCC 70 85 4.5 LCC
DDR2 SDRAM
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
64Mx8 (K4T51083QE) Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 8 215 8 35 40 30 12 60 115 145 115 4 8 215 800@CL=5 CE7 85 95 5 8 35 40 30 12 60 115 145 115 4 8 180 LE7 800@CL=6 CF7 85 95 5 8 35 40 30 12 55 105 135 110 4 8 180 LF7 667@CL=5 CE6 75 90 5 8 30 35 30 12 50 90 110 110 4 8 180 LE6 533@CL=4 CD5 75 85 4.5 8 30 35 30 12 50 85 100 105 4 LD5 400@CL=3 CCC 70 85 4.5 LCC mA mA mA mA mA mA mA mA mA mA mA mA mA
Unit
Notes
32Mx16 (K4T51163QE) Symbol
IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 8 280 8 35 40 30 12 60 135 190 115 4 8 280 800@CL=5 CE7 95 115 5 8 35 40 30 12 60 135 190 115 4 8 240 LE7 800@CL=6 CF7 95 115 5 8 35 40 30 12 55 120 170 110 4 8 240 LF7 667@CL=5 CE6 90 110 5 8 30 35 30 12 50 105 140 110 4 8 215 LE6 533@CL=4 CD5 90 105 4.5 8 30 35 30 12 50 100 135 110 4 LD5 400@CL=3 CCC 90 105 4.5 LCC mA mA mA mA mA mA mA mA mA mA mA mA mA
Unit
Notes
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K4T51043QE K4T51083QE K4T51163QE 12.0 Input/Output capacitance
Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Symbol CCK CDCK CI CDI CIO CDIO DDR2-400 DDR2-533 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 4.0 0.5 DDR2-667 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 2.0 0.25 3.5 0.5
DDR2 SDRAM
DDR2-800 Min 1.0 x 1.0 x 2.5 x Max 2.0 0.25 1.75 0.25 3.5 0.5 pF pF pF pF pF pF
Units
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 C < TOPER < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter Refresh to active/Refresh command time Average periodic refresh interval tRFC tREFI 0 C TCASE 85C 85 C < TCASE 95C Symbol 256Mb 75 7.8 3.9 512Mb 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb 327.5 7.8 3.9 Units ns s s
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed Bin (CL - tRCD - tRP) Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tCK, CL=6 tRCD tRP tRC tRAS min 5 3.75 2.5 12.5 12.5 57.5 45 DDR2-800(E7) 5-5-5 max 8 8 8 70000 min 3.75 3 2.5 15 15 60 45 DDR2-800(F7) 6-6-6 max 8 8 8 70000 5 3.75 3 15 15 60 45 DDR2-667(E6) 5-5-5 min max 8 8 8 70000 5 3.75 3.75 15 15 60 45 DDR2-533(D5) 4-4-4 min max 8 8 8 70000 5 5 15 15 55 40 DDR2-400(CC) 3-3-3 min max 8 8 70000 ns ns ns ns ns ns ns ns Units
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13.3 Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Symbol tAC tDQSCK tCH tCL tHP tCK tDH(base) tDS(base) DDR2-800 min - 400 - 350 0.45 0.45 min(tCL,t CH) 2500 125 50 0.6 0.35 x tAC min 2* tAC min x x tHP tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 250 175 0.9 0.4 7.5 max 400 350 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 200 300 x 0.25 x x x x x 0.6 x x x 1.1 0.6 x DDR2-667 min -450 -400 0.45 0.45 min(tCL, tCH) 3000 175 100 0.6 0.35 x tAC min 2*tAC min x x tHP tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 275 200 0.9 0.4 7.5 max +450 +400 0.55 0.55 x 8000 x x x x tAC max tAC max DDR2-533 min -500 -450 0.45 0.45 min(tCL, tCH) 3750 225 100 0.6 0.35 x tAC min max +500 +450 0.55 0.55 x 8000 x x x x tAC max tAC max
DDR2 SDRAM
DDR2-400 min -600 -500 0.45 0.45 min(tCL, tCH) 5000 275 150 0.6 0.35 x tAC min max +600 +500 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 350 450 x 0.25 x x x x x 0.6 x x x 1.1 0.6 x
Units ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns
Notes
20,21 24 15,16, 17,20 15,16, 17,21
Control & Address input pulse width for each input tIPW DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK tDIPW tHZ tLZ(DQS) tLZ(DQ)
27 27 22 21
tAC max 2* tACmin tAC max 2* tACmin 240 340 x 0.25 x x x x x 0.6 x x x 1.1 0.6 x x x tHP tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 7.5 300 400 x 0.25 x x x x x 0.6 x x x 1.1 0.6 x x x tHP tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 475 350 0.9 0.4 7.5
DQS-DQ skew for DQS and associated DQ sigtDQSQ nals DQ hold skew factor DQ/DQS output hold time from DQS tQHS tQH
First DQS latching transition to associated clock tDQSS edge DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH(base) tIS(base) tRPRE tRPST
19
14,16, 18,23 14,16, 18,22 28 28 12
Active to active command period for 1KB page tRRD size products
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Parameter Symbol DDR2-800 min 10 35 45 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) 2 tAC(max) + 0.7 x x x x x x max x DDR2-667 min 10 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 2 tAC(min) 2 tAC(max) +0.7 x x x x x max x DDR2-533 min 10 37.5 50 2 15 WR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 2 tAC(min) 2 x x x x x max x
DDR2 SDRAM
DDR2-400 min 10 37.5 50 2 15 WR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL 3 2 2 tAC(max) +1 x x x x x max x Units ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK tCK ns ns tCK ns ns tCK tCK 12 ns ns 24 26 13, 25 9 9, 10 36 23 33 11 Notes 12
Active to active command period for 2KB page tRRD size products Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command tCCD tWR tDAL tWTR tRTP tXSNR tXSRD
Exit precharge power down to any non-read comtXP mand Exit active power down to read command Exit active power down to read command (slow exit, lower power) CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay tXARD tXARDS
t
CKE
tAOND t
AON
tAC(max) tAC(min) +1
tAONPD tAOFD t
2tCK + 2tCK+tA tAC(min)+ tAC(min)+ 2tCK+tAC tAC(min)+ tAC(min)+ 2tCK+tAC tAC(max) C(max)+ 2 2 (max)+1 2 2 (max)+1 +1 1 2.5 tAC(min) 2.5 tAC(max) + 0.6 2.5 tAC(min) 2.5 tAC(max) + 0.6 2.5 tAC(min) 2.5 tAC(max) + 0.6 2.5 tAC(min) 2.5 tAC(max) + 0.6
AOF
tAOFPD
2.5tCK + 2.5tCK+t 2.5tCK+ 2.5tCK+ tAC(min)+ tAC(min)+ tAC(min)+ tAC(min)+ tAC(max) AC(max) tAC(max) tAC(max) 2 2 2 2 +1 +1 +1 +1 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH 12 3 8 0 tIS+tCK +tIH
tANPD tAXPD tOIT
Minimum time clocks remains ON after CKE asyntDelay chronously drops LOW
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K4T51043QE K4T51083QE K4T51163QE 14.0 General notes, which may apply for all AC parameters
DDR2 SDRAM
1. DDR2 SDRAM AC timing reference load Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ DQS DQS RDQS RDQS
DUT
Output 25 Timing reference point Figure 1 - AC Timing Reference Load
VTT = VDDQ/2
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 2. Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc) to VIL(ac),max for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in Figure 2. VDDQ DUT
DQ DQS, DQS RDQS, RDQS
Output Test point 25
VTT = VDDQ/2
Figure 2 - Slew Rate Test Load
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4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 to 10 k resistor to insure proper operation.
DQS/ DQS DQ
DQS DQS tWPRE
VIH(ac)
tDQSH
tDQSL
tWPST
VIH(dc)
D
VIL(ac)
D
D
VIL(dc)
D tDH
VIH(dc)
tDS
VIH(ac)
tDS
tDH DMin
DM
DMin
DMin
VIL(ac)
DMin
VIL(dc)
Figure 3 - Data Input (Write) Timing
tCH CK
tCL
CK/CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ
Figure 4 - Data Output (Read) Timing
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions. 6. All voltages are referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
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K4T51043QE K4T51083QE K4T51163QE 15.0 Specific Notes for dedicated AC parameters
DDR2 SDRAM
1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. 2. AL = Additive Latency. 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 x tCK or 2 x nCK) is required irrespective of operating frequency. 5. Timings are specified with command/address input slew rate of 1.0 V/ns. 6. Timings are specified with DQs, DM, and DQS's (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns. 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1.0 V/ns in single ended mode. 8. Data setup and hold time derating.
Table 1 - DDR2-400/533 tDS/tDH derating with differential data strobe
tDS, tDH Derating Values of DDR2-400, DDR2-533 (ALL units in `ps', the note applies to entire Table) DQS,DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ Siew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 125 83 0 tDH 45 21 0 3.0 V/ns tDS 125 83 0 -11 tDH 45 21 0 -14 2.0 V/ns tDS 125 83 0 -11 -25 tDH 45 21 0 -14 -31 1.8 V/ns tDS 95 12 1 -13 -31 tDH 33 12 -2 -19 -42 1.6 V/ns tDS 24 13 -1 -19 -43 tDH 24 10 -7 -30 -59 1.4V/ns tDS 25 11 -7 -31 -74 tDH 22 5 -18 -47 -89 1.2V/ns tDS 23 5 -19 -62 -127 tDH 17 -6 -35 -77 -140 1.0V/ns tDS 17 -7 -50 -115 tDH 6 -23 -65 -128 0.8V/ns tDS 5 -38 -103 tDH -11 -53 -116
Table 2 - DDR2-667/800 tDS/tDH derating with differential data strobe
tDS, tDH Derating Values for DDR2-667, DDR2-800 (ALL units in `ps', the note applies to entire Table) DQS,DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 100 67 0 tDH 45 21 0 3.0 V/ns tDS 100 67 0 -5 tDH 45 21 0 -14 2.0 V/ns 100 67 0 -5 -13 45 21 0 -14 -31 1.8 V/ns tDH 33 12 -2 -19 -42 79 12 7 -1 -10 1.6 V/ns tDS 24 19 11 2 -10 tDH 24 10 -7 -30 -59 1.4V/ns tDS 31 23 14 2 -24 22 5 -18 -47 -89 1.2V/ns tDH 17 -6 -35 -77 -140 35 26 14 -12 -52 1.0V/ns tDS 38 26 0 -40 tDH 6 -23 -65 -128 0.8V/ns tDS 38 12 -28 tDH -11 -53 -116 tDS tDH tDS tDH tDS
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Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe
DDR2 SDRAM
tDS1, tDH1 Derating Values for DDR2-400, DDR2-533(All units in `ps'; the note applies to the entire table) DQS Single-ended Slew Rate 2.0 V/ns tDS 1 2.0 1.5 1.0 DQ Slew rate V/ns 0.9 0.8 0.7 0.6 0.5 0.4 188 146 63 tDH 1 188 167 125 1.5 V/ns tDS 1 167 125 42 31 tDH 1 146 125 83 69 1.0 V/ns tDS 1 125 83 0 -11 -25 tDH 1 63 42 0 -14 -31 0.9 V/ns tDS 1 81 -2 -13 -27 -45 tDH 1 43 1 -13 -30 -53 0.8 V/ns tDS 1 -7 -18 -32 -50 -74 tDH 1 -13 -27 -44 -67 -96 0.7 V/ns tDS 1 -29 -43 -61 -85 -128 tDH 1 -45 -62 -85 -114 -156 0.6 V/ns tDS 1 -60 -78 -102 -145 -210 tDH 1 -86 -109 -138 -180 -243 0.5 V/ns tDS 1 -108 -138 -175 -240 tDH 1 -152 -181 -223 -286 0.4 V/ns tDS 1 -183 -226 -291 tDH 1 -246 -288 -351
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the tDS and tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(dc) to ac region', use nominal slew rate for derating value (See Figure 5 for differential data strobe and Figure 6 for single-ended data strobe.) If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 7 for differential data strobe and Figure 8 for single-ended data strobe) Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded 'dc level to VREF(dc) region', use nominal slew rate for derating value (see Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe) Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
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DQS
DQS tDS VDDQ tDH tDS tDH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max tVAC VSS TF Setup Slew Rate= Falling Signal VREF(dc) - Vil(ac)max TF
TR Setup Slew Rate Vih(ac)min - VREF(dc) = Rising Signal TR
Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS)
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DQS
Note1
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
tDS VDDQ
tDH
tDS
tDH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max
VSS TF Setup Slew Rate= VREF(dc) - Vil(ac)max Falling Signal TF
TR Setup Slew Rate Vih(ac)min - VREF(dc) = Rising Signal TR
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS)
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DQS
DQS VDDQ tDS tDH nominal line VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS TF Setup Slew Rate tangent line[Vih(ac)min - VREF(dc)] Rising Signal= TR TR tDS tDH
VIH(ac) min
Setup Slew Rate tangent line[VREF(dc) - Vil(ac)max] Falling Signal = TF
Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS)
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DQS
Note1
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
VDDQ
tDS
tDH nominal line
tDS
tDH
VIH(ac) min VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS Setup Slew Rate tangent line[Vih(ac)min - VREF(dc)] Rising Signal= TR TR
TF
Setup Slew Rate tangent line[VREF(dc) - Vil(ac)max] Falling Signal = TF Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 8 - IIIustration of tangent line for tDS (single-ended DQS)
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DDR2 SDRAM
DQS
DQS VDDQ tDS tDH tDS tDH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate nominal slew rate
VIL(ac) max
VSS TR Hold Slew Rate VREF(dc) - Vil(dc)max Rising Signal = TR TF
Hold Slew Rate Vih(dc)min - VREF(dc) = Falling Signal TF
Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS)
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DQS
Note1
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
VDDQ
tDS
tDH
tDS
tDH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate nominal slew rate
VIL(ac) max
VSS TR Hold Slew Rate VREF(dc) - Vil(dc)max Rising Signal = TR TF
Hold Slew Rate Vih(dc)min - VREF(dc) = Falling Signal TF
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS)
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DQS
DQS tDS VDDQ tDH tDS tDH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line tangent line
nominal line
VIL(ac) max
VSS TR Hold Slew Rate tangent line [ VREF(dc) - Vil(dc)max ] Rising Signal = TR Hold Slew Rate tangent line [ Vih(dc)min - VREF(dc) ] Falling Signal = TF TF
Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS)
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DQS
Note1
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
VDDQ
tDS
tDH
tDS
tDH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line tangent line
nominal line
VIL(ac) max
VSS TR tangent line [ VREF(dc) - Vil(dc)max ] TR TF
Hold Slew Rate Rising Signal =
Hold Slew Rate tangent line [ Vih(dc)min - VREF(dc) ] Falling Signal = TF
Note : DQS signal must be monotonic between Vil(dc)max and Vih(dc)min.
Figure 12 - IIIustration of tangent line for tDH (single-ended DQS)
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9. tIS and tIH (input setup and hold) derating
DDR2 SDRAM
Table 4 - Derating values for DDR2-400, DDR2-533
tIS, tIH Derating Values for DDR2-400, DDR2-533 CK, CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 Command/ Address Slew rate(V/ns) 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS +217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 -1420 1.5 V/ns tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 tIS +247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 -1390 1.0 V/ns tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Table 5 - Derating values for DDR2-667, DDR2-800
tIS and tIH Derating Values for DDR2-667, DDR2-800 CK, CK Differential Slew Rate 2.0 V/ns tIS 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 Command/ Address Slew rate(V/ns) 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +150 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS +180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 1.5 V/ns tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 tIS +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940 1.0 V/ns tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065
DDR2 SDRAM
Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the tIS and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded 'VREF(dc) to ac region', use nominal slew rate for derating value (see Figure 13). If the actual signal is later than the nominal slew rate line anywhere between shaded 'VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 14). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slewrate line between shaded 'dc to VREF(dc) region', use nominal slew rate for derating value (see Figure 15). If the actual signal is earlier than the nominal slew rate line anywhere between shaded 'dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 16). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in Tables 4 and 5, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
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CK
CK tIS VDDQ tIH tIS tIH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max
VSS TF Setup Slew Rate VREF(dc) - Vil(ac)max = Falling Signal TF
TR Setup Slew Rate Vih(ac)min - VREF(dc) = Rising Signal TR
Figure 13 - IIIustration of nominal slew rate for tIS
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DDR2 SDRAM
CK
CK tIS VDDQ tIH nominal line VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS Setup Slew Rate= Rising Signal tangent line[Vih(ac)min - VREF(dc)] TR TR tIS tIH
VIH(ac) min
TF
Setup Slew Rate tangent line[VREF(dc) - Vil(ac)max] = Falling Signal TF
Figure 14 - IIIustration of tangent line for tIS
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CK
CK tIS VDDQ tIH tIS tIH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate nominal slew rate
VIL(ac) max
VSS TR Hold Slew Rate VREF(dc) - Vil(dc)max Rising Signal = TR TF
Hold Slew Rate Vih(dc)min - VREF(dc) = Falling Signal TF
Figure 15 - IIIustration of nominal slew rate for tIH
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CK
CK tIS VDDQ tIH tIS tIH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line tangent line
nominal line
VIL(ac) max
VSS TR Hold Slew Rate tangent line [ VREF(dc) - Vil(dc)max ] Rising Signal = TR Hold Slew Rate tangent line [ Vih(dc)min - VREF(dc) ] Falling Signal = TF TF
Figure 16 - IIIustration of tangent line for tIH
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10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces. 12. tQH = tHP - tQHS, where : tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle. 14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. The clock frequency is allowed to change during self refresh mode or precharge power-down mode. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT LOW if tCK = 5 ns. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. 18. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Figure 17 shows a method to calculate the point when device is no longer driving (tHZ), or beginsdriving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQS and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each treated as single-ended signal. 19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 17 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
VOH + x mV VOH + 2x mV tHZ tRPST end point T2 T1 VOL + 2x mV VOL + x mV
VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - 2x mV T1 T2
tHZ,tRPST end point = 2*T1-T2
tLZ,tRPRE begin point = 2*T1-T2
Figure 17 - Method for calculating transitions and endpoints
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20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18. 21. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
DQS DQS
tDS
tDH
tDS
tDH
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
Figure 18 - Differential input waveform timing - tDS and tDH 22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. See Figure 19. 23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test. See Figure 19.
CK CK
tIS
tIH
tIS
tIH
VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS
Figure 19 - Differential input waveform timing - tIS and tIH
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24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency.
DDR2 SDRAM
25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 26. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be monotonic between Vil(dc)max and Vih(dc)min. 27. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 28. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 29. These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 30. These parameters are measured from a data strobe signal ((L/U/R)DQS/DQS) crossing to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 31. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/ R)DQS/DQS) crossing. 32. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5 is valid even if (Tm+5 - Tm) is less than 15ns due to input clock jitter. 33. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [ps] / tCK(avg) [ps] }, where WR is the value programmed in the mode register set. 34. New units, 'tCK(avg)' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK(avg)' represents the actual tCK(avg) of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, 'tCK' is used for both concepts. ex) tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min. 35. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. DDR2-667 Min -125 -100 -250 -200 -175 -225 -250 -250 -350 -450 -125 Max 125 100 250 200 175 225 250 250 350 450 125 DDR2-800 Min -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 -100 Max 100 80 200 160 150 175 200 200 300 450 100
Parameter Clock period jitter Clock period jitter during DLL locking period Cycle to cycle clock period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n = 6 ... 10, inclusive Cumulative error across n cycles, n = 11 ... 50, inclusive Duty cycle jitter
Symbol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty)
units ps ps ps ps ps ps ps ps ps ps ps
Notes 35 35 35 35 35 35 35 35 35 35 35
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Definitions :
- tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N tCK(avg) = where
DDR2 SDRAM
tCKj
/N
j=1 N = 200
- tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N tCH(avg) = where
tCHj
/(N x tCK(avg))
j=1 N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses. N tCL(avg) = where
tCLj
/(N x tCK(avg))
j=1 N = 200
- tJIT(duty) tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg). tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} where, tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200} tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200} - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing. - tJIT(cc), tJIT(cc,lck) tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles : tJIT(cc) = Max of |tCKi+1 - tCKi| tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing. - tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per) tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg). i+n-1 tERR(nper) =
tCKj
- n x tCK(avg)
j=1 n=2 n=3 n=4 n=5 6 n 10 11 n 50 for for for for for for tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per)
where
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K4T51043QE K4T51083QE K4T51163QE
DDR2 SDRAM
36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Parameter Absolute clock Period Absolute clock HIGH pulse width Absolute clock LOW pulse width Symbol tCK(abs) tCH(abs) tCL(abs) Min tCK(avg),min + tJIT(per),min tCH(avg),min x tCK(avg),min + tJIT(duty),min tCL(avg),min x tCK(avg),min + tJIT(duty),min Max tCK(avg),max + tJIT(per),max tCH(avg),max x tCK(avg),max + tJIT(duty),max tCL(avg),max x tCK(avg),max + tJIT(duty),max Units ps ps ps
Example: For DDR2-667, tCH(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = Min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock HIGH time; tCL(abs) is the minimum of the actual instantaneous clock LOW time; 38. tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 40. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps and tERR(6-10per),max = + 293 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 ps - 293 ps = - 693 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(610per),min = 400 ps + 272 ps = + 672 ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 ps - 293 ps = - 1193 ps and tLZ(DQ),max(derated) = 450 ps + 272 ps = + 722 ps. 41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated) = tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. 42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max = + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. 43. When the device is operated with input clock jitter, this parameter needs to be derated by { - tJIT(duty),max - tERR(6-10per),max } and { tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6- 10per),max = + 293 ps, tJIT(duty),min = 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) = tAOF,max + { - tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps.
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DDR2 SDRAM
44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45, the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK or tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK) where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls. 45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg) tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg) tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg)) tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg)) where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls. Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However tAC values used in the equations shown above are from the timing parameter table and are not derated. Thus the final derated values for tAOF are; tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max } tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }
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Rev. 1.8 July 2007

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